Applications in the mm-wave frequency regime have gained significant interest in the past few years due to the rapid advancement in low cost semiconductor technologies like silicon germanium (SiGe) and fine geometry complementary metal-oxide semiconductor (CMOS) processes. Availability of high speed bipolar and MOS transistors has led to a growing demand for integrated circuits for mm-wave applications at 60 GHz, 77 GHz, and 80 GHz and also beyond 100 GHz. Such applications include, for example, automotive radar and multi-gigabit communication systems.
As the operating frequencies of RF systems continue to increase, the generation of signals at such high frequencies poses a major challenge. Oscillators that operate at high frequencies may suffer from a poor phase noise performance and a low output power in some systems. Moreover, frequency dividers used in phase locked loops (PLLs) at such high frequencies may consume a significant amount of power.
One way in which the challenges of generating high frequency signal is addressed is through the use of frequency multipliers. For example, a voltage controlled oscillator (VCO) combined with a frequency doubler may be used to generate a high frequency signal. By operating the VCO at one-half of the output frequency enables a system to generate a high frequency signal having better phase noise and higher output power than a VCO configured to operate at the full output frequency. However, the design of frequency multipliers at mm-wave frequencies poses its own set of design challenges including the ability to provide a high output power and the ability to reject the fundamental input frequency.